The present invention relates generally to methods of and circuits for measuring a semiconductor-on-insulator (SOI) device transient and more particularly to methods and circuits for measuring the charge dump of an individual transistor in an SOI device.
Traditional semiconductor-on-insulator (SOI) integrated circuits typically have a silicon substrate with a buried oxide (BOX) layer disposed thereon. An active silicon layer is disposed on the opposite side of the BOX layer from the silicon substrate. Within the active silicon layer, active devices, such as transistors, are formed in active regions. The size and placement of the active regions are defined by shallow trench isolation (STI) regions. As a result of this arrangement, the active devices are isolated from the silicon substrate by the BOX layer. In addition, a body region of each SOI transistor does not have body contacts and is therefore floating.
Such SOI structures offer potential advantages over bulk chips for the fabrication of high performance integrated circuits for digital circuitry. Such digital circuitry is typically made from partially-depleted metal oxide semiconductor field effect transistors (MOSFETs). These SOI structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to the floating body charging effects. These performance gains result from: a) no connection being made to the channel region, and b) charging of the floating body providing access toward a majority of carriers which dynamically lowers the threshold voltage and increased drain current. Devices, such as metal oxide silicon field effect transistors (MOSFET), have a number of advantages when formed on SOI wafers versus bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance that results in improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and thus higher packing density due to ease of isolation; absence of latch-up; lower voltage applications; and higher soft error upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Although there are significant advantages associated with SOI technology, there are some disadvantages as well. For example, there is an inability to reliably measure the SOI transient of a single MOSFET on an SOI substrate so as to better control the performance of a typical million plus (1,000,000+) transistor microprocessor.
In view of the aforementioned disadvantages, there is a need for a method and circuit for measuring the SOI transient of a single MOSFET in an SOI device.
According to the invention, a method is disclosed for measuring a charge dump current of a transistor device. The transistor device, typically a MOSFET on an SOI has a source, a drain, and a gate. The method comprises the steps of a) connecting a measuring circuit to the drain, the measuring circuit having a trip-point switching circuit with its trip point set to an initial trip point voltage that should not cause the switching circuit to trip; b) charging the drain to a supply voltage; c) applying a high-to-low voltage pulse to the source; d) detecting whether or not the trip-point switching circuit has tripped; e) when the switching circuit has not tripped, adjusting the trip point Voltage in increments and repeating steps b, c and d until a threshold trip point is reached where the trip-point switching circuit does trip; and f) recording the threshold trip point whereby the dump charge through the transistor device can be determined.
According to the invention, the method further includes the steps of: h) determining a first charge at the drain at the threshold trip voltage; i) determining a second charge at the drain at the supply voltage; and j) subtracting the first charge from the second charge to determine the total dump charge from the drain to the source.
Further according to the invention, the method includes the step of charging drain to the supply voltage by charging a capacitor connected to the drain and to ground to the supply voltage with a switchable connection.
According to the invention, a system for measuring the charge dump current of a transistor device on an SOI is disclosed. The device has a source, a drain, and a gate all formed on a substrate. The system has a measuring circuit connected to the drain. The measuring circuit includes a capacitor connected between the drain and ground, a switchable connection to apply a supply voltage to the capacitor, and a trip-point switching circuit connected to the drain. Circuit means are provided for setting the trip point of the trip-point switching circuit to an initial trip point voltage that should not cause the switching circuit to trip. A switch device is provided for applying a high-to-low voltage pulse to the source. A buffer and output reading device are provided for detecting whether or not the trip-point switching circuit has tripped. Circuit adjustment structure is provided for adjusting the trip point Voltage in increments until a threshold trip point is reached where the trip-point switching circuit does trip. A recording device is provided to record the threshold trip point whereby the dump charge through the transistor device can be determined.
According to the invention, another embodiment is provided for measuring a charge dump of a transistor device under test, the device under test having a source, a drain, and a gate. The method comprises the steps of: connecting a measuring circuit to the drain, the measuring circuit including a plurality of trip-point switching circuits, each of the switching circuits with their trip point set to an initial trip point voltage different from the other switching circuits; charging the drain to a supply voltage; applying a high-to-low voltage pulse to the source; detecting whether or not each of the trip-point switching circuits has tripped; recording the highest trip point just below when the switching circuit has tripped; recording the lowest trip point just above when the switching circuit has tripped; and estimating the threshold trip point between the highest trip point recorded and the lowest trip point recorded whereby the dump charge through the transistor device can be determined.
Further according to the invention, the method includes the steps of: determining a first charge at the drain at the threshold trip voltage; determining a second charge at the drain at the supply voltage; and subtracting the first charge from the second charge to determine the total dump charge from the drain to the source.
According to the invention, an alternative embodiment of a system for measuring the charge dump current of a transistor device on an SOI is disclosed. As set forth above, the device has a source, a drain, and a gate all formed on a substrate. The system comprises a measuring circuit with a plurality of trip-point switching circuits, each of the switching circuits with their trip point set to an initial trip point voltage different from the other switching circuits. Charging means are provided for charging the drain to a supply voltage. Switch means apply a high-to-low voltage pulse to the source. Circuit means detect whether or not the each of the trip-point switching circuits has tripped. Circuit means record the highest trip point just below when the switching circuit has tripped and the lowest trip point just above when the switching circuit has tripped. Device means estimate the threshold trip point between the highest trip point recorded and the lowest trip point recorded whereby the dump charge through the transistor device can be determined.